NXP Semiconductors /MIMXRT1021 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_B0_05

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_AD_B0_05

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

MUX_MODE=ALT0, SION=DISABLED

Description

SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: JTAG_TRSTB of instance: jtag_mux

1 (ALT1): Select mux mode: ALT1 mux port: FLEXCAN1_RX of instance: flexcan1

2 (ALT2): Select mux mode: ALT2 mux port: USDHC1_CD_B of instance: usdhc1

3 (ALT3): Select mux mode: ALT3 mux port: QTIMER2_TIMER1 of instance: qtimer2

4 (ALT4): Select mux mode: ALT4 mux port: ENET_MDC of instance: enet

5 (ALT5): Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1

6 (ALT6): Select mux mode: ALT6 mux port: USB_OTG1_ID of instance: anatop

7 (ALT7): Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_B0_05

Links

() ()